The strategy of enhancing the function of an integrated circuit by reducing its critical dimensions, known as scaling, has been a key to faster performance and more densely packed integrated circuits. However, as semiconductor devices continue to become smaller in size, the devices must continue to be able to be made with reduced dimensions and still function at the required specifications.
As the device dimensions shrink, problems arise which need to be addressed. These problems, for example, include high resistances and capacitances within the device which, in turn, contribute to delay problems.
By way of example, in 70 nanometer technology, high resistance is directly attributable to, amongst other features, the narrow dimensions of the vertical metal lines which connect metal on different layers, Mx and Mx+1. In a typical device using such technology, the metal lines are on the order of sub micron sizes, e.g., 1/10 of a micron in height. This reduced size results in less metal within the device and, hence, an increase in the overall resistance of the device. Also, at these dimensions, electron scattering from sidewalls and grain boundaries adds significantly to the resistance of the metal interconnect.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.